Developing linear error models for analog devices

Techniques are presented for developing linear error models for analog and mixed-signal devices. A simulation program developed to understand the modeling process is described, and results of simulations are presented. Methods for optimizing the size of empirical error models based on simulated error analyses are included. Once established, the models can be used in a comprehensive approach for optimizing the testing of the subject devices. Models are developed using data from a group of 13-bit A/D converters and compared with the simulation results