• DocumentCode
    1104327
  • Title

    Minimization of Exclusive or and Logical Equivalence Switching Circuits

  • Author

    Mukhopadhyay, Amar ; Schmitz, Greg

  • Author_Institution
    IEEE
  • Issue
    2
  • fYear
    1970
  • Firstpage
    132
  • Lastpage
    140
  • Abstract
    This paper is an attempt to develop minimization algorithms for switching circuits based on Reed-Muller canonic forms. In particular, algorithms are presented for obtaining minimal modulo 2 or complement modulo 2 sum-of- products (or sums) expressions of any arbitrary single-output or multiple-output switching function with fixed polarities of the input variables.
  • Keywords
    APL, cellular logic arrays, maximal cliques of a graph, miniimization algorithms, modulo 2 sum-of- products (or sums), Reed-Muller canonic forms.; Circuit synthesis; Codes; Computer languages; Input variables; Iterative algorithms; Large scale integration; Logic arrays; Minimization methods; Programmable logic arrays; Switching circuits; APL, cellular logic arrays, maximal cliques of a graph, miniimization algorithms, modulo 2 sum-of- products (or sums), Reed-Muller canonic forms.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/T-C.1970.222878
  • Filename
    1671471
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1104327