DocumentCode
1104357
Title
Fast Multipliers
Author
Habibi, A. ; Wintz, P.A.
Issue
2
fYear
1970
Firstpage
153
Lastpage
157
Abstract
A number of schemes for implementing a fast multiplier are presented and compared on the basis of speed, complexity, and cost. A parallel multiplier designed using the carry-save scheme and constructed from 74 series integrated circuits is described. This multiplier multiplies 10-bit by 12-bit binary numbers with a worst- case multiplication time of 520 ns. The cost of the integrated circuits was less than $ 500.
Keywords
Dadda´s multiplier, digital multipliers, fast multipliers, parallel multipliers, simultaneous multipliers, Wallace´s multipliers.; Costs; Counting circuits; NASA; Dadda´s multiplier, digital multipliers, fast multipliers, parallel multipliers, simultaneous multipliers, Wallace´s multipliers.;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/T-C.1970.222881
Filename
1671474
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