A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector

Author

Wei-Sung Chang ; Po-Chun Huang ; Tai-Cheng Lee

Author_Institution

Dept. of Electr. Eng. & Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

49

Issue

12

fYear

2014

fDate

Dec. 2014

Firstpage

2964

Lastpage

2975

Abstract

A low-noise divider-less PLL, employing a subsampling locked loop, samples the VCO output by a digital pulse-width modulator (DPWM) to perform fractional-N operation. The frequency synthesizer achieves a low in-band phase noise of -112 dBc/Hz at a 2.3 GHz output frequency. The analysis for the frequency synthesizer, especially for the nonlinear characteristics of the circuits, is proposed. Fabricated in a 0.18 μm CMOS technology, the frequency synthesizer consumes 9.6 mA and achieves figure-of-merit of -239.1 dB, corresponding to 266 fs rms jitter.

Keywords

CMOS digital integrated circuits; frequency synthesizers; phase detectors; phase locked loops; voltage-controlled oscillators; CMOS technology; VCO output; current 9.6 mA; digital pulse width modulator; fractional-N divider less phase locked loop; frequency 2.3 GHz; frequency synthesizer; size 0.18 mum; subsampling locked loop; subsampling phase detector; Delays; Modulation; Noise; Phase locked loops; Quantization (signal); Synthesizers; Voltage-controlled oscillators; Digital pulse-width modulator (DPWM); SSPLL; divider-less; fractional-N synthesizer; noise folding; phase-locked loop (PLL);

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2014.2359670

Filename

6924788