DocumentCode
1105137
Title
High-speed GaAs frequency dividers using a self-aligned dual-level double lift-off substitution gate MESFET process
Author
Chang, M.F. ; Lee, S.J. ; Walton, E.R. ; Lee, C.P. ; Ryan, F.J. ; Vahrenkamp, R.P. ; Kirkpatrick, C.G.
Author_Institution
Rockwell International Corporation, Thousand Oaks, CA, USA
Volume
6
Issue
6
fYear
1985
fDate
6/1/1985 12:00:00 AM
Firstpage
279
Lastpage
281
Abstract
A new self-aligned substitution gate process, which uses a dual-level resist (photoresist/polymethylmethacrylate (PMMA)) and a double lift-off technique has been successfully developed for the fabrication of MESFET circuits on 3-in GaAs wafers. Good device uniformity (20-mV standard deviation of threshold voltage) and excellent device characteristics ( 
mS/mm) were obtained. Single-clocked divide-by-four frequency dividers with direct-coupled FET logic (DCFL) and five-gate delay design were fabricated by the above process. The maximum input frequency measured was 4.4 GHz. The minimum power dissipation was a 0.55-mW/gate with a speed-power product of 39 fJ.
mS/mm) were obtained. Single-clocked divide-by-four frequency dividers with direct-coupled FET logic (DCFL) and five-gate delay design were fabricated by the above process. The maximum input frequency measured was 4.4 GHz. The minimum power dissipation was a 0.55-mW/gate with a speed-power product of 39 fJ.Keywords
Delay; FETs; Fabrication; Frequency conversion; Gallium arsenide; Logic design; Logic devices; MESFET circuits; Resists; Threshold voltage;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/EDL.1985.26125
Filename
1485278
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