High-Throughput Digit-Level Systolic Multiplier Over Based on Irreducible Trinomials

In this brief, we propose high-throughput digitlevel systolic structure for area-delay-efficient implementation of multiplier over GF(2^m) based on irreducible trinomials. We have proposed a digit-level multiplication algorithm, which allows us to compute a set of d (where d is the digit size) partial products in parallel in each processing element (PE) during each cycle and accumulate them across the systolic pipeline in reduced form. To enhance the throughput rate of the proposed structure, we feed the reduced operands and accumulated partial products to the PEs by independent systolic channels that reduces the critical path to (T_A + T_X + T_R), where T_A, T_X, and T_R refer to the propagation delays of AND gate, XOR gate, and bit register, respectively. From synthesis results, it is found that the proposed multiplier involves significantly lower area-time complexity and higher throughput than the existing competing designs.