Title :
Classification and identification of nonrobust untestable path delay faults
Author :
Cheng, Kwang-Ting ; Chen, Hsj-Chuan
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
fDate :
8/1/1996 12:00:00 AM
Abstract :
Recently published results have shown that, for many circuits, only a small percentage of path delay faults is robust testable, Among the robust untestable faults, a significant percentage is not nonrobust testable either. In this paper, we take a closer look at the properties of these nonrobust untestable faults with the goal of determining whether and how these faults should be tested. We define a path delay fault to be functional redundant (f-redundant) if, regardless of the delays at all other signals, the circuit performance will not be determined by the path. These paths are false paths-regardless of the delays of all signals. Therefore, these paths cannot and need not be tested. We present a sufficient condition for functional redundancy. We will show that nonrobust untestable faults are not necessarily f-redundant. For those nonrobust untestable but functional irredundant (f-irredundant) faults, the corresponding path may become a true path, and thus may determine the circuit performance under the faulty condition. We present an efficient algorithm for identifying f-redundant path delay faults. Results show that a significant percentage of path delay faults are f-redundant for ISCAS´85 benchmark circuits. Identification of f-redundant faults has two important applications: 1) it provides a more realistic fault coverage measure (as the number of detected faults divided by the total number of f-irredundant faults), 2) For circuits with a large number of paths, testing only a subset of paths becomes a common practice. The path selection process can be guided to avoid selecting f-redundant paths. To illustrate this application, we present an algorithm for selecting a set of f-irredundant path delay faults that includes at least one of the longest f-irredundant paths for each signal in the circuits
Keywords :
automatic testing; combinational circuits; delays; fault diagnosis; integrated circuit testing; logic testing; redundancy; ISCAS´85 benchmark circuits; circuit performance; combinational circuits; fault coverage measure; functional irredundant faults; functional redundant fault; nonrobust untestable path delay faults; Benchmark testing; Circuit faults; Circuit optimization; Circuit testing; Delay; Electrical fault detection; Fault diagnosis; Redundancy; Robustness; Sufficient conditions;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on