DocumentCode
1105642
Title
Cell geometry effect on IGT latch-up
Author
Yilmaz, H.
Author_Institution
General Electric Company, Syracuse, NY
Volume
6
Issue
8
fYear
1985
fDate
8/1/1985 12:00:00 AM
Firstpage
419
Lastpage
421
Abstract
The effect of the emitter cell geometry on insulated gate transistor (IGT) performance has been investigated. The three-dimensional well resistances (emitter shunting resistance) of the square, circular, stripe, and multiple surface short (MSS) have been calculated. The MSS cell geometry has the lowest emitter shunting resistance. As a result, MSS cell has the highest latch-up current capability. It has been experimentally proven that the stripe cell has extremely high latch-up current, and the MSS cell design is current limited. The IGT´s with circular and square cell have the lowest latch-up current capability.
Keywords
Buffer layers; Geometry; Helium; Insulation; P-n junctions; Strips; Surface resistance; Switches; Temperature; Thyristors;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/EDL.1985.26176
Filename
1485329
Link To Document