• DocumentCode
    1105731
  • Title

    High-Speed Computer Multiplication Using a Multiple-Bit Decoding Algorithm

  • Author

    Ling, H.

  • Author_Institution
    IEEE
  • Issue
    8
  • fYear
    1970
  • Firstpage
    706
  • Lastpage
    709
  • Abstract
    This paper presents a method of performing the binary multiplication beyond the scheme of multiple ADD and SHIFT. The binary multiplication algorithm will be discussed first, followed by block decoding method, logic implementation, hardware consideration, and two examples which are at the end of the discussion.
  • Keywords
    Block decoding technique, fast multiplication, high-speed computer logic, high-speed multiplication, parallel multiplication.; Concurrent computing; Decoding; Equations; Hardware; High performance computing; Logic; Transfer functions; Block decoding technique, fast multiplication, high-speed computer logic, high-speed multiplication, parallel multiplication.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/T-C.1970.223020
  • Filename
    1671613
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1105731