• DocumentCode
    1105767
  • Title

    Wire sizing as a convex optimization problem: exploring the area-delay tradeoff

  • Author

    Sapatnekar, Sachin S.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
  • Volume
    15
  • Issue
    8
  • fYear
    1996
  • fDate
    8/1/1996 12:00:00 AM
  • Firstpage
    1001
  • Lastpage
    1011
  • Abstract
    An efficient solution to the wire sizing problem using the Elmore delay model is proposed. Two formulations of the problem are put forth. In the first, the minimum interconnect delay is sought, while in the latter, we minimize the net delay under delay constraints at the leaf nodes; previous approaches solve only the former problem. Theoretical results on these problems are proved, and two algorithms are presented. One is a sensitivity-based heuristic, while the other is a rigorous convex optimization problem. It is shown experimentally that the sensitivity-based heuristic gives near-optimal results with reasonable runtimes. A smooth area-delay tradeoff is shown, and results are presented to illustrate the fact that sizing for minimum delay is not a good engineering goal. Instead, a delay goal of even 15% over the minimum provides significantly better engineering solutions
  • Keywords
    circuit layout CAD; delays; network topology; sensitivity analysis; wiring; area-delay tradeoff; convex optimization problem; delay constraints; delay goal; engineering solutions; leaf nodes; minimum interconnect delay; net delay; sensitivity-based heuristic; wire sizing; Capacitance; Career development; Delay effects; Geometry; Integrated circuit interconnections; Runtime; Timing; Tree data structures; Upper bound; Wire;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.511579
  • Filename
    511579