DocumentCode
1105806
Title
Dynamic data retention and implied design criteria for floating-body SOI DRAM
Author
Suh, Dongwook ; Fossum, Jerry G. ; Pelella, Mario M.
Author_Institution
Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA
Volume
17
Issue
8
fYear
1996
Firstpage
385
Lastpage
387
Abstract
A physical MOSFET model in SOISPICE is used to characterize dynamic data retention in PD/SOI DRAM cells. Simulations show that transient parasitic BJT current underlies peculiar data retention, and they suggest how periodic body discharge effected by data refresh with a high flatband-voltage cell transistor can render PD/SOI technology viable and attractive for gigabit DRAM applications.
Keywords
DRAM chips; MOS memory circuits; MOSFET; semiconductor device models; silicon-on-insulator; PD/SOI technology; SOISPICE; data refresh; design criteria; dynamic RAM cells; dynamic data retention; floating-body SOI DRAM; gigabit DRAM applications; high flatband-voltage cell transistor; periodic body discharge; physical MOSFET model; transient parasitic BJT current; Coupling circuits; Equations; Hysteresis; MOSFET circuits; Microelectronics; Partial discharges; Predictive models; Radiative recombination; Random access memory; Threshold voltage;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.511583
Filename
511583
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