A Novel Parallel Binary Counter Design with Parity Prediction and Error Detection Scheme

In binary counters, the parity bit is not preserved when the data undergo the counting operation. It is necessary to predict the parity bit that should be used with the correct result. A special design has been devised to share as much hardware as possible between the counter and the parity prediction circuit. This reduces the number of logic gates and gives a more efficient design. The scheme involves the use of the first 0 detection for both the counting operation and the parity prediction.