Abstract :
In this paper we develop an algorithm to design a switching network using only gates which represent negative functions. The number of gates in the network is minimized under the conditions that 1) the network consists of two levels, and 2) no fan-in restriction on each gate is imposed.
Keywords :
Conjoint, logical design, minimal cover, MOS, negative gates, network with minimum number of gates, supplementary columns, truth table.; Algorithm design and analysis; Computer science; FETs; Input variables; Integrated circuit technology; MOS integrated circuits; Manufacturing; Minimization; Network synthesis; Power dissipation; Conjoint, logical design, minimal cover, MOS, negative gates, network with minimum number of gates, supplementary columns, truth table.;
