• DocumentCode
    1106345
  • Title

    Fabrication of five-layered interconnection CMOS LSI using polyimide resist insulators

  • Author

    Kakuda, Nobuhiko ; Wada, Tsutomu ; Naito, Noboru ; Mutoh, Nobuo

  • Author_Institution
    NTT, Musashino Electrical Communication Laboratory, Tokyo, Japan
  • Volume
    6
  • Issue
    11
  • fYear
    1985
  • fDate
    11/1/1985 12:00:00 AM
  • Firstpage
    589
  • Lastpage
    590
  • Abstract
    A five-metal-layered interconnection 20k gate CMOS LSI is fabricated using polyimide resist insulators. It is proved that the use of polyimide resist insulators results in excellent planarization, small residual stress, a smooth via profile, and a reduction in the number of steps required for the process. As a result, this technique appears to be a practical means of fabricating five or more layered interconnection systems.
  • Keywords
    CMOS technology; Curing; Fabrication; Insulation; Integrated circuit interconnections; Large scale integration; Metallization; Planarization; Polyimides; Resists;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/EDL.1985.26240
  • Filename
    1485393
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1106345