• DocumentCode
    1106861
  • Title

    Effective Wire Models for X-Architecture Placement

  • Author

    Chen, Tung-Chieh ; Chuang, Yi-Lin ; Chang, Yao-Wen

  • Author_Institution
    Nat. Taiwan Univ., Taipei
  • Volume
    27
  • Issue
    4
  • fYear
    2008
  • fDate
    4/1/2008 12:00:00 AM
  • Firstpage
    654
  • Lastpage
    658
  • Abstract
    In this paper, we derive the X-half-perimeter wirelength (XHPWL) model for X-architecture placement and explore the effects of three different wire models on X-architecture placement, including the Manhattan-half-perimeter wirelength (MHPWL) model, the XHPWL model, and the X-Steiner wirelength (XStWL) model. For min-cut partitioning placement, we apply the XHPWL and XStWL models to the generalized net-weighting method that can exactly model the wirelength after partitioning by net weighting. For analytical placement, we smooth the XHPWL function using log-sum-exp functions to facilitate analytical placement. This paper shows that both the XHPWL and XStWL models can reduce the X wirelength effectively. In particular, our results reveal the effectiveness of the X architecture on wirelength reduction during placement and, thus, the importance of the study on the X-placement algorithms, which is different from the results given in the work of Ono et al. which suggests that the X-architecture placement might not improve the X-routing wirelength over the Manhattan-architecture placement.
  • Keywords
    integrated circuit design; Manhattan-architecture placement; Manhattan-half-perimeter wirelength model; X-Steiner wirelength model; X-architecture placement; X-half-perimeter wirelength; log-sum-exp functions; min-cut partitioning placement; net weighting partitioning; wire models; Circuit optimization; Costs; Delay; Geometry; Integrated circuit interconnections; Partitioning algorithms; Pins; Routing; Wire; Wiring; Min-cut; Steiner tree; X architecture; net weighting; partitioning; physical design; placement;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2008.917959
  • Filename
    4475243