DocumentCode
1106895
Title
A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits
Author
Breuer, Melvin A.
Author_Institution
IEEE
Issue
11
fYear
1971
Firstpage
1364
Lastpage
1370
Abstract
Two procedures are presented for generating fault detection test sequences for large sequential circuits. In the adaptive random procedure one can achieve a tradeoff between test generation time, length, and percent of circuit tested. An algorithmic path-sensitizing procedure is also presented. Both procedures employ a three-valued logic system. Some experimental results are given.
Keywords
Digital logic simulation, fault detection test generation, random test generation, S-algorithm, sequential circuits, three-valued simulation.; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Electrons; Fault detection; Fault diagnosis; Logic testing; Sequential analysis; Sequential circuits; Digital logic simulation, fault detection test generation, random test generation, S-algorithm, sequential circuits, three-valued simulation.;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/T-C.1971.223140
Filename
1671733
Link To Document