Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations

This paper presents the first published algorithm to simultaneously optimize both short- and long-path timing in a field-programmable gate array (FPGA): the routing cost valleys (RCV) algorithm. RCV consists of the following two components: a new slack-allocation algorithm that determines both a minimum and a maximum delay budget for each circuit connection and a new router that strives to meet and, if possible, surpass these connection-delay constraints. RCV improves both long- and short-path timing slacks significantly versus an earlier computer-aided design system, showing the importance of an integrated approach that simultaneously optimizes considering both types of timing constraints. It is able to meet long- and short-path timing constraints on all 157 peripheral component interconnect cores tested, while an earlier algorithm failed to achieve timing on 75% of the cores. Even in cases where there are no short-path timing constraints, RCV outperforms a state-of-the-art FPGA router and improves the maximum clock speed of circuits by an average of 3.2% (and up to 24.7%).