Design, Test, and Repair of MLUT (Memristor Look-Up Table) Based Asynchronous Nanowire Reconfigurable Crossbar Architecture

The recently proposed nanoscale asynchronous crossbar architecture based on memristor-based look up table (MLUT) combines the advantages of nanoscale memristor crossbar technology and clockless logic paradigm for viable nanoscale computing. Potential technical merits of the proposed MLUT architecture includes: 1) better manufacturability due to structural simplicity and regularity; 2) improved robustness over PVT (process-voltage-temperature) variations; 3) event-driven low-power/noise asynchronous operation; and 4) encoding-level logic inversion. In spite of having numerous merits over the clocked counterparts and previous asynchronous designs, it is bound to have inevitable defects and faults due to nondeterministic and unconventional nanoscale assembly and operation. In order to overcome defect issues in the proposed MLUT-based nanoscale asynchronous crossbar architecture, there is a need to develop efficient design, test, and repair techniques. Typical approach so far has been to test every crosspoint on each crossbar MLUT exhaustively; this is not only laborious but is also prohibitively time and space consuming for designs involving large number of MLUTs. This paper introduces a novel testing scheme based on “Divide and Conquer” approach to efficiently locate the defective memristors in a MLUT. The proposed testing scheme leverages upon a special current additive property of the memristor-based multiplexer. It performs binary isolation of regions, reducing the search space by half whenever applicable. Numerical simulations clearly demonstrate that the approach is generic, deterministic, and scalable. A faster MLUT programming technique and a repair technique utilizing partially defective MLUTs are also proposed and extensively validated through parametric simulations.