DocumentCode :
1106931
Title :
GfXpress: A Technique for Synthesis and Optimization of \\hbox {GF}(2^{m}) Polynomials
Author :
Jabir, Abusaleh M. ; Pradhan, Dhiraj K. ; Mathew, Jimson
Author_Institution :
Oxford Brookes Univ., Oxford
Volume :
27
Issue :
4
fYear :
2008
fDate :
4/1/2008 12:00:00 AM
Firstpage :
698
Lastpage :
711
Abstract :
This paper presents an efficient technique for synthesis and optimization of the polynomials over GF(2m), where to is a nonzero positive integer. The technique is based on a graph-based decomposition and factorization of the polynomials, followed by efficient network factorization and optimization. A technique for efficiently computing the coefficients of the polynomials over GF(pm), where p is a prime number, is first presented. The coefficients are stored as polynomial graphs over GF(pm). The synthesis and optimization is initiated from this graph-based representation. The technique has been applied to minimize multipliers over the fields GF(2k), where k = 2,...,8, generated with all the 51 primitive polynomials in the 0.18-mum CMOS technology with the help of the Synopsys design compiler. It has also been applied to minimize combinational exponentiation circuits, parallel integer adders and multipliers, and other multivariate bit- as well as word-level polynomials. The experimental results suggest that the proposed technique can reduce area, delay, and power by significant amounts. We also observed that the technique is capable of producing 100% testable circuits for stuck-at faults.
Keywords :
circuit analysis computing; circuit testing; fault diagnosis; graph theory; polynomials; CMOS technology; GfXpress; Synopsys design compiler; combinational exponentiation circuit; graph-based decomposition; graph-based representation; multipliers; multivariate bit; network factorization; nonzero positive integer; parallel integer adders; polynomial factorization; polynomial graphs; polynomial optimization; polynomial synthesis; size 0.18 mum; stuck-at faults; testable circuit; word-level polynomial; Circuit synthesis; Circuit testing; Delay; Design optimization; Galois fields; Hardware; Network synthesis; Optimizing compilers; Polynomials; Very large scale integration; Decision diagrams; decomposition; finite or Galois fields; polynomials; synthesis and optimization; testing; verification;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2008.917586
Filename :
4475250
Link To Document :
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