Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation

Process variations cause design performance to become unpredictable in deep submicrometer technologies. Several statistical techniques (timing analysis, gate sizing, and buffer insertion) have been proposed to counter these variations during the optimization phase of the design flow to get a better timing yield. Another interesting approach to improve the timing yield is postsilicon-tunable (PST) clock tree. In this paper, we propose such an integrated framework that performs simultaneous statistical gate sizing in the presence of PST clock-tree buffers for minimizing binning yield loss (YL) and tunability costs by determining the ranges of delay tuning to be provided at each buffer. The simultaneous gate sizing and PST-buffer range determination problem is proved to be a convex-stochastic programming formulation under longest path-delay constraints and, hence, solved optimally. We further extend the formulation into a heuristic to additionally consider shortest path-delay constraints. We make experimental comparisons using nominal gate sizing followed by PST-buffer management using the work of Tsai as a base case. We take the solution obtained from this approach and perform the following: 1) sensitivity-based statistical gate sizing while retaining the PST clock tree and 2) simultaneous gate sizing and PST-buffer range determination as proposed in this paper. On an average, the base-case approach gave 23% timing YL, the sensitivity approach gave 15% YL, whereas our proposed algorithm gave only 4% YL.