Title :
Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs
Author :
Lin, Chung-Wei ; Chen, Szu-Yu ; Li, Chi-Feng ; Chang, Yao-Wen ; Yang, Chia-Lin
Author_Institution :
Nat. Taiwan Univ., Taipei
fDate :
4/1/2008 12:00:00 AM
Abstract :
Given a set of pins and a set of obstacles on a plane, an obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) connects these pins, possibly through some additional points (called the Steiner points), and avoids running through any obstacle to construct a tree with a minimal total wirelength. The OARSMT problem becomes more important than ever for modern nanometer IC designs which need to consider numerous routing obstacles incurred from power networks, prerouted nets, IP blocks, feature patterns for manufacturability improvement, antenna jumpers for reliability enhancement, etc. Consequently, the OARSMT problem has received dramatically increasing attention recently. Nevertheless, considering obstacles significantly increases the problem complexity, and thus, most previous works suffer from either poor quality or expensive running time. Based on the obstacle-avoiding spanning graph, this paper presents an efficient algorithm with some theoretical optimality guarantees for the OARSMT construction. Unlike previous heuristics, our algorithm guarantees to find an optimal OARSMT for any two-pin net and many higher pin nets. Extensive experiments show that our algorithm results in significantly shorter wirelengths than all state-of-the-art works.
Keywords :
integrated circuit design; trees (mathematics); minimal total wirelength; nanometer IC; obstacle-avoiding rectilinear Steiner tree construction; spanning graphs; two-pin net; Computer science; Heuristic algorithms; Large-scale systems; Manufacturing; NP-complete problem; Pins; Routing; Steiner trees; Timing; Tree graphs; Physical design; Steiner tree; routing; spanning tree;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2008.917583