Modeling and Analysis of Planar-Gate Electrostatic Capacitance of 1-D FET With Multiple Cylindrical Conducting Channels

This paper presents accurate analytical models to calculate the electrostatic gate capacitance of 1-D field-effect transistors (FETs) with multiple cylindrical conducting channels. Gate capacitance C_gg is decomposed into three major components: 1) capacitance C_gc between the gate and the parallel cylindrical conducting channels (the number of channels ges 1) in dual-layer dielectric materials; 2) outer fringe capacitance C_of between the gate and the source/drain cylinder conductors; and 3) coupling capacitance C_gtg between the adjacent gates. A realistic planar-gate structure with high-k gate dielectric material is considered in this paper, including the screening effect of the parallel conductors and different dielectric materials on capacitance. An accuracy of 10% is achieved from the analytic models, compared with the values that were simulated by 3-D numerical field solvers. Using a simple analytical expression for the gate delay that includes the parasitic capacitance and screening of multiple parallel conducting channels, this paper also shows that both increasing the number of channels per gate and reducing the gate height are effective ways to improve device speed.