• DocumentCode
    1107025
  • Title

    Fast Dummy-Fill Density Analysis With Coupling Constraints

  • Author

    Xiang, Hua ; Deng, Liang ; Puri, Ruchir ; Chao, Kai-Yuan ; Wong, Martin D F

  • Author_Institution
    IBM, Yorktown Heights
  • Volume
    27
  • Issue
    4
  • fYear
    2008
  • fDate
    4/1/2008 12:00:00 AM
  • Firstpage
    633
  • Lastpage
    642
  • Abstract
    In modern very large scale integration manufacturing processes, dummy fills are widely used to adjust local metal density in order to improve layout uniformity and yield optimization. However, the introduction of a large amount of dummy features also affects wire electrical properties. In this paper, we propose the first coupling-constrained dummy-fill analysis algorithm which identifies feasible locations for dummy fills such that the fill-induced coupling capacitance can be bounded within the given coupling threshold of each wire segment. A speedup approach is presented based on the cache concept. The algorithm also makes efforts to maximize ground dummy fills, which are more robust and predictable. The output of the algorithm can be treated as the upper bound for dummy-fill insertion, and it can be easily adopted in density models to guide dummy-fill insertion without disturbing the existing design.
  • Keywords
    VLSI; capacitance; chemical mechanical polishing; circuit layout; coupled circuits; planarisation; wires (electric); coupling constraints; coupling-constrained dummy-fill analysis algorithm; density models; dummy-fill insertion; fast dummy-fill density analysis; fill-induced coupling capacitance; ground dummy fills; layout uniformity; metal density adjustment; very large scale integration manufacturing; wire electrical properties; wire segment; yield optimization; Algorithm design and analysis; Capacitance; Chaos; Constraint optimization; Coupling circuits; Foundries; Manufacturing processes; Rails; Very large scale integration; Wire; Chemical mechanical planarization (CMP); coupling; dummy fills;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2008.917963
  • Filename
    4475260