Abstract :
A straightforward efficient computer algorithm for synthesizing multiple-output NAND (NOR) switching networks is presented which takes practical fan-in and fan-out limitations of logic gates into account. The algorithm is highly iterative and hence is very suitable for realizing large-size switching functions by a digital computer. The algorithm has been programmed in Fortran and a great deal of statistical data has been obtained to demonstrate its efficiency in terms of gate count as well as computing time. It is also efficient for hand execution
Keywords :
Algorithm, combinational logic, design automation, factoring, fan-in limit; fan-out limit, minimization techniques, multiple-output, NAND ( NOR) synthesis, switching circuits, switching functions.; Algorithm design and analysis; Circuit synthesis; Computer networks; Design automation; Iterative algorithms; Logic design; Logic gates; Minimization; Network synthesis; Switching circuits; Algorithm, combinational logic, design automation, factoring, fan-in limit; fan-out limit, minimization techniques, multiple-output, NAND ( NOR) synthesis, switching circuits, switching functions.;
