Modeling of Strained CMOS on Disposable SiGe Dots: Strain Impacts on Devices´ Electrical Characteristics

We proposed a new nonplanar disposable SiGe dot (d-Dot) MOSFET based on Si-on-nothing technology. The new device concepts´ relies on self-assembled single-crystalline d-Dot. The d-Dot MOSFET is prone to a particularly high strain/stress, both from the underlaying SiGe 3-D islands and from the stressed capping layers. We show that more than 80% and 50% higher mobilities of holes and electrons, respectively, can be obtained, as indicated by 3-D simulations performed throughout the entire fabrication process. Significant improvements in drive currents, transit frequencies, and the short channel effects are demonstrated using 2-D device simulation.