A Heuristic Procedure for the Partitioning and Mapping of Computer Logic Graphs

Author

Russo, Roy L. ; Oden, Peter H. ; Wolff, Peter K., Sr.

Author_Institution

IEEE

Issue

12

fYear

1971

Firstpage

1455

Lastpage

1462

Abstract

A heuristic procedure for partitioning or mapping a set of interconnected blocks into subsets called modules is presented. Each module may be constrained in terms of the number of blocks and/or the number of intermodule connections that it can accommodate. The procedure allows given blocks to be mapped to more than one module in order to reduce the number of modules required if such reduction is desirable. Results obtained from applying the procedure, by means of a computer program, to the partitioning and mapping of computer logic gates into chips and cards are presented.

Keywords

Computer-aided design, computer-based design, design automation, graph decomposECon, hardware packaging, heuristic algorithm, logic mapping, logic partitioning, logic segmentation, packaging of logic networks.; Algorithm design and analysis; Application software; Costs; Hardware; Integrated circuit interconnections; Large scale integration; Logic design; Logic gates; Packaging; Strontium; Computer-aided design, computer-based design, design automation, graph decomposECon, hardware packaging, heuristic algorithm, logic mapping, logic partitioning, logic segmentation, packaging of logic networks.;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/T-C.1971.223157

Filename

1671750