Title :
On a Pin Versus Block Relationship For Partitions of Logic Graphs
Author :
Landman, Bernard S. ; Russo, Roy L.
Author_Institution :
IEEE
Abstract :
Partitions of the set of blocks of a computer logic graph, also called a block graph, into subsets called modules demonstrate that a two-region relationship exists between P, the average number of pins per module, and B, the average number of blocks per module. In the first region, P = KBr, where K is the average number of pins per block and 0.57 ≤ r ≤ 0.75. In the second region, that is, where the number of modules is small (i.e., 1-5), P is less than predicted by the above formula and is given by a more complex relationship. These conclusions resulted from controlled partitioning experiments performed using a computer program to partition four logic graphs varying in size from 500 to 13 000 circuits representing three different computers. The size of a block varied from one NOR circuit in one of the block graphs to a 30-circuit chip in one of the other block graphs.
Keywords :
Hardware implementation, logic package pin requirements, logic partitioning, pins versus blocks relation, pins versus circuits relation.; Hardware; Helium; Integrated circuit interconnections; Joining processes; Logic circuits; Logic design; Packaging; Pins; Registers; Size control; Hardware implementation, logic package pin requirements, logic partitioning, pins versus blocks relation, pins versus circuits relation.;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/T-C.1971.223159