Substrate bias effects on transiently triggered latchup in bulk CMOS

Bulk and p⁺/p^-epitaxial CMOS wafers with and without off-chip substrate bias generation have been examined for latchup immunity to ramped power excitation and transient spike. It is found that a substrate bias applied to a topside contact is more effective than to a backside contact in producing a latchup-free operation. Epitaxial silicon is found to be superior to the nonepitaxial case. A lumped-element model is used to derive the holding voltage and explain the observations.