DocumentCode
1107416
Title
Impact of a Process Variation on Nanowire and Nanotube Device Performance
Author
Paul, Bipul C. ; Fujita, Shinobu ; Okajima, Masaki ; Lee, Thomas H. ; Wong, H. S Philip ; Nishi, Yoshio
Author_Institution
Stanford Univ., Stanford
Volume
54
Issue
9
fYear
2007
Firstpage
2369
Lastpage
2376
Abstract
In this paper, we present an in-depth analysis of the nanowire and nanotube device performance under process variability. Although every process parameter variation drastically affects the conventional MOSFET performance, we found that nanowire/nanotube FETs are significantly less sensitive to many process parameter variations due to their inherent device structures and geometric properties. It is observed that a two-input nand gate with nanowire or nanotube FETs shows a more than four times less performance variation than its bulk MOSFET counterpart and about two times less than FinFET devices at the 45 and 32 nm technologies, respectively. In other words, nanowire/nanotube FETs will have a larger margin for process parameter variations than bulk and FinFET devices for an allowable performance variation limit. While it is evident that process variations are going to be a major limiting factor for conventional MOSFET devices in future generations, this analysis is expected to further encourage nanowire and nanotube research for high-performance circuit applications.
Keywords
MOSFET; carbon nanotubes; nanotube devices; nanowires; FinFET devices; bulk MOSFET; carbon nanotube FET; device performance; nanowire FET; process variation; size 32 nm; size 45 nm; Controllability; Digital circuits; FETs; Fabrication; FinFETs; MOSFET circuits; Nanoscale devices; Nanotube devices; Performance analysis; Silicon; CNFET performance under variation; nanowire FET performance under variation; process variation;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2007.901882
Filename
4294235
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