DocumentCode
1108259
Title
Mixed analogue/digital phase picking algorithm in oversampling burst-mode clock phase alignment
Author
Mélange, C. ; Baekelandt, B. ; Demuytere, P. ; Bauwelinck, J. ; Van Renterghem, K. ; De Ridder, T. ; Qiu, X.Z. ; Vandewege, J.
Author_Institution
INTEC/IMEC, Ghent Univ., Ghent
Volume
45
Issue
13
fYear
2009
Firstpage
694
Lastpage
695
Abstract
A novel mixed analogue/digital design of a phase picking algorithm in an oversampling clock phase recovery is presented. The proposed approach results in reduced processing time, improved integrability with analogue front-end and low noise generation. Simulations of a 10 Gbit/s burst-mode clock phase alignment circuit in a 0.25 m SiGe BiCMOS process, show a simulated processing delay of only 280 ps.
Keywords
BiCMOS integrated circuits; Ge-Si alloys; mixed analogue-digital integrated circuits; optical communication equipment; synchronisation; BiCMOS process; SiGe; analogue front-end; bit rate 10 Gbit/s; burst-mode clock phase alignment circuit; low noise generation; mixed analogue-digital phase picking algorithm; optical fibre networks; oversampling burst-mode clock phase alignment; oversampling clock phase recovery; size 0.25 micron; time 280 ps;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el.2009.3525
Filename
5117399
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