Process-dependent properties of three-dimensional capacitors

Capacitance per unit of cell area in silicon MOS IC technologies can be increased by etching convolutions into the semiconductor surface beneath the electrode [1]-[4]. These convolutions are typically formed via directional dry processing (reactive ion etching (RIE)). Energetic plasma process steps, however, have been reported to result in degradation of capacitor MOS properties in both planar [5]-[9] and three-dimensional [3], [4], [10] devices. In our experiments, planar devices formed on etched surfaces display MOS behavior that is normal in all respects when standard pre-oxidation cleaning is performed. Three-dimensional devices, however, can suffer a non-trivial degradation of dielectric breakdown voltage. The degradation is found to result from field enhancement accompanying identifiable topographical features, and is not an inherent result of RIE processing. RIE and post-RIE processing parameters influence the degree of degradation. TEM examination of three-dimensional devices is employed to characterize the physical nature of RIE-fabricated devices, and the observations are correlated with electrical behavior.