DocumentCode
1108422
Title
Interface effects of SIPOS passivation
Author
Tong, David W. ; Benjamin, John L. ; Van Dell, Ron W.
Author_Institution
General Electric Company, Schenectady, NY
Volume
33
Issue
6
fYear
1986
fDate
6/1/1986 12:00:00 AM
Firstpage
779
Lastpage
787
Abstract
Electrical characterization of metal-semi-insulating polycrystalline silicon (SIPOS)-Si samples have been carried out using 
, 
, and 
techniques. Bulk resistivity and interface properties have been examined. The results indicate that annealing can give rise to a current barrier at the SIPOS-Si interface that constitutes another mechanism for interface charge formation as distinct from interface states. This current barrier-induced interface charge can lead to significant spreading of the depletion zone on test diodes. With SIPOS bulk resistivity greater than 108Ω . cm, the interface electrical properties are shown to have greater influence than bulk SIPOS properties on device behavior.
, , and techniques. Bulk resistivity and interface properties have been examined. The results indicate that annealing can give rise to a current barrier at the SIPOS-Si interface that constitutes another mechanism for interface charge formation as distinct from interface states. This current barrier-induced interface charge can lead to significant spreading of the depletion zone on test diodes. With SIPOS bulk resistivity greater than 108Ω . cm, the interface electrical properties are shown to have greater influence than bulk SIPOS properties on device behavior.Keywords
Annealing; Capacitance-voltage characteristics; Chemical vapor deposition; Conductivity; Diodes; Insulation; Passivation; Silicon devices; Stability; Testing;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/T-ED.1986.22568
Filename
1485785
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