DocumentCode
1108782
Title
Serial Adders with Overflow Correction
Author
Berg, R.O. ; Kinney, L.L.
Author_Institution
IEEE
Issue
6
fYear
1971
fDate
6/1/1971 12:00:00 AM
Firstpage
668
Lastpage
671
Abstract
A method of implementing two single-bit adders is discussed. These adders can be used individually to realize the conventional functions of serial addition and serial multiplication on a pair of operands, or they can be cascaded to allow the serial addition of three operands for forming the product of complex numbers. In either case, the circuits will detect the occurrence of an overflow or the generation of the number minus one, and they will allow an addition to be rescaled by outputting the correct bits during the additional shifts, whether the addition overflowed or not.
Keywords
Cascaded adders, overflow detection and correction, parallel processing, serial addition.; Adders; Arithmetic; Circuit synthesis; Electrons; Encoding; Flip-flops; Large scale integration; Parallel processing; Sequential circuits; Switching circuits; Cascaded adders, overflow detection and correction, parallel processing, serial addition.;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/T-C.1971.223321
Filename
1671914
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