Abstract :
In this note, we develop an algorithm to design a two-level switching network composed of negative gates with no fan-in restriction imposed on them. The resulting network is such that it minimizes the cost function h(G, 1), a monotone nondecreasing function of G and I, where G is the total number of gates and I is the total number of interconnections in the network. In other words, the earlier work is generalized so that the number of interconnections may be included in its cost criterion. The algorithm is then extended to the multiple output network design.
Keywords :
Compatible sets, gate-interconnection minimization, MOS integrated circuits, multiple output networks, negative gates, set covering problems, switching networks, two-level networks.; Algorithm design and analysis; Cost function; Integrated circuit interconnections; Integrated circuit technology; MOS integrated circuits; Mathematics; Minimization methods; Physics; Switching circuits; Compatible sets, gate-interconnection minimization, MOS integrated circuits, multiple output networks, negative gates, set covering problems, switching networks, two-level networks.;
