A VLSI chip for the winograd/Prime factor algorithm to compute the discrete Fourier transform

There is an extensive literature about computing the discrete Fourier transform and the hardware implementations of the different algorithms. In this paper, we propose a radically different approach based on the so-called small n algorithms and several different iteration methods. Our approach will result in fully pipelined bit serial architectures which require no control units. The area is about the minimum possible, and the overall delay is within an optimal order magnitude. An essential ingredient of these implementations is the use of digit on-line adder and multiplier cells.