• DocumentCode
    1109192
  • Title

    Design of Diagnosable Iterative Arrays

  • Author

    Landgraff, R.W. ; Yau, S.S.

  • Author_Institution
    IEEE
  • Issue
    8
  • fYear
    1971
  • Firstpage
    867
  • Lastpage
    877
  • Abstract
    One-and two-dimensional iterative arrays of identical cells are becoming more important in the design of digital systems using large-scale integrated circuits because of the advantages that they provide in design, fabrication, and testing. Since arrays containing hundreds or thousands of gates on one chip are now considered possible, the task of finding procedures for the testing of such arrays from their edges is of concern to both the users and the manufactures. The iterative nature of cellular arrays sometimes makes it possible to derive test schedules of reasonable length.
  • Keywords
    Cells, design, fault detection, fault location, iterative arrays, one-dimensional, techniques, two-dimensional.; Circuit faults; Circuit testing; Costs; Digital systems; Fabrication; Fault detection; Job shop scheduling; Logic arrays; Logic testing; System testing; Cells, design, fault detection, fault location, iterative arrays, one-dimensional, techniques, two-dimensional.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/T-C.1971.223363
  • Filename
    1671956