DocumentCode :
110923
Title :
The Role of Geometry Parameters and Fin Aspect Ratio of Sub-20nm SOI-FinFET: An Analysis Towards Analog and RF Circuit Design
Author :
Mohapatra, S.K. ; Pradhan, K.P. ; Singh, D. ; Sahu, P.K.
Author_Institution :
Dept. of Electr. Eng., Nat. Inst. of Technol., Rourkela, India
Volume :
14
Issue :
3
fYear :
2015
fDate :
May-15
Firstpage :
546
Lastpage :
554
Abstract :
Nowadays FinFETs integrated into complex circuit applications can fulfill the demand of smartphones and tablets for better performance and make chips that can compute faster. This paper studies the impact of HFin and WFin variations on various performance matrices including static as well as dynamic figures of merit (FOMs). With the help of aspect ratio (WFin/HFin), the device is branched into three parts, i.e., FinFET, Trigate, and Planar MOSFET. This unique report is a presentation of a detailed analysis about the impact of fin height (HFin) and width (WFin) on various performances including the dc as well as ac FOMs. The static or low-frequency performances like threshold voltage (Vth), on current (Ion), off current (Ioff ), power dissipation, transconductance (gm), output conductance (gd), transconductance generation factor (TGF = gm /ID), early voltage (VEA), gain (AV), and dynamic or high-frequency performances as gate capacitance (Cgg), cutoff frequency (fT), output resistance (R0), intrinsic delay are systematically presented with the variation of device geometry parameters. The results presented in this paper can be of great help to device engineers in designing 3-D devices as per their requirement.
Keywords :
MOSFET; silicon-on-insulator; HFin variations; RF circuit design; SOI-FinFET; WFin variations; analog circuit design; cutoff frequency; dynamic figures of merit; fin aspect ratio; fin height; fin width; gate capacitance; geometry parameters; intrinsic delay; output conductance; output resistance; smartphones; tablets; threshold voltage; transconductance generation factor; FinFETs; Logic gates; Mathematical model; Performance evaluation; Semiconductor process modeling; Transconductance; Aspect Ratio; Device Performance; FinFET; Planar MOSFET; Process Parameters; Trigate;
fLanguage :
English
Journal_Title :
Nanotechnology, IEEE Transactions on
Publisher :
ieee
ISSN :
1536-125X
Type :
jour
DOI :
10.1109/TNANO.2015.2415555
Filename :
7064756
Link To Document :
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