DocumentCode
1109516
Title
Wafer-Level Integration Technique of Surface Mount Devices on a Si-Wafer With Vibration Energy and Gravity Force
Author
Sudou, Minoru ; Takao, Hidekuni ; Sawada, Kazuaki ; Ishida, Makoto
Author_Institution
Toyohashi Univ. of Technol., Toyohashi
Volume
30
Issue
3
fYear
2007
Firstpage
457
Lastpage
463
Abstract
This paper reports about a novel wafer-level integration technique of discrete surface mount devices (SMDs). It enables wafer-level mounting of plural kinds of SMDs on a silicon (Si)-wafer using vibration and gravity force. Deep holes with 400-m depth are formed on the surface of a Si-wafer by deep reactive ion etching process after general integrated circuit process for positioning of SMDs. A non-conductive adhesive (CYTOP) are coated on the deep holes and it is used to fix the aligned SMDs. SMDs are distributed on a Si-wafer mounted on vibration generator, and then a vibration is applied. The SMDs migrate due to the reduced friction between the wafer surface, and they drop into the holes on the silicon wafer. The size of the holes has an appropriate clearance to the size of SMD. In order to align two or more kinds of SMDs, sizes of the deep holes on a Si-wafer are adjusted to the size of each SMD. SMDs with the largest size are dropped into the holes first, and then the secondary large SMDs are dropped into the holes with the corresponding size. SMDs are finally connected electrically by wire bonding at the final step. In the experiment, two different sizes of SMD were successfully mounted into all the holes on a Si-wafer automatically. This technology will be a wafer-level process technology which is very promising to integrate two or more kinds of discrete elements.
Keywords
adhesives; lead bonding; silicon; sputter etching; surface mount technology; wafer level packaging; Si - Interface; Si wafer; deep reactive ion etching process; general integrated circuit process; gravity force; nonconductive adhesive; silicon wafer; surface mount devices; vibration energy; vibration generator; wafer-level integration technique; wafer-level mounting; wafer-level process technology; wire bonding; Etching; Friction; Gravity; Integrated circuit technology; Nonconductive adhesives; Packaging; Radio frequency; Silicon; Wafer bonding; Wire; Embedded passive integrated circuits (emPIC); passive integration; silicon integrated circuit (IC) technology;
fLanguage
English
Journal_Title
Components and Packaging Technologies, IEEE Transactions on
Publisher
ieee
ISSN
1521-3331
Type
jour
DOI
10.1109/TCAPT.2007.898742
Filename
4295169
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