Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers

Author

Gondi, Srikanth ; Razavi, Behzad

Author_Institution

Univ. of California, Los Angeles

Volume

42

Issue

9

fYear

2007

Firstpage

1999

Lastpage

2011

Abstract

Two equalizer filter topologies and a merged equalizer/CDR circuit are described that operate at 10 Gb/s in 0.13-mum CMOS technology. Using techniques such as reverse scaling, passive peaking networks, and dual- and triple-loop adaptation, the prototypes adapt to FR4 trace lengths up to 24 inches. The equalizer/CDR circuit retimes the data with a bit error rate of 10^-13 while consuming 133 mW from a 1.6-V supply.

Keywords

CMOS integrated circuits; adaptive equalisers; clocks; radio receivers; synchronisation; CMOS serial-link receivers; bit error rate; bit rate 10 Gbit/s; clock and data recovery; dual-loop adaptation; equalization technique; equalizer filter topologies; merged equalizer/CDR circuit; passive peaking networks; power 133 mW; reverse scaling; size 0.13 mum; triple-loop adaptation; voltage 1.6 V; CMOS technology; Circuit topology; Clocks; Crosstalk; Equalizers; Filters; Frequency; Intersymbol interference; Propagation losses; Prototypes; Adaptive equalization; DFE; FFE; analog equalization; broadband receivers; high-speed links; lossy channel; reverse scaling;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2007.903076

Filename

4295193