Abstract :
In this paper, the systematic design and analysis of a CMOS performance-optimized distributed low-noise amplifier (DLNA) comprising bandwidth-enhanced cascode cells will be presented. Each cascode cell employs an inductor between the common-source and common-gate devices to enhance the bandwidth, while reducing the high-frequency input-referred noise. The noise analysis and optimization of the DLNA accurately accounts for the impact of thermal noise of line terminations and all device noise sources of each CMOS cascode cell including flicker noise, correlated gate-induced noise and channel thermal noise on the overall noise figure. A three-stage performance-optimized wideband DLNA has been designed and fabricated in a 0.18-mum SiGe process, where only MOS transistors were utilized. Measurements of the test chip show a flat noise figure of 2.9 dB, a forward gain of 8 dB, and input and output return losses below -12 dB and -10 dB, respectively, across the 7.5 GHz UWB band. The circuit exhibits an average IIP3 of -3.55 dBm. The 872 mum times 872 mum DLNA chip consumes 12 mA of current from a 1.8-V DC voltage.
Keywords :
CMOS integrated circuits; Ge-Si alloys; MOSFET; integrated circuit design; low noise amplifiers; thermal noise; ultra wideband communication; MOS transistor; SiGe process; UWB distributed LNA; bandwidth-enhanced cascode cell; common-gate device; common-source device; current 12 mA; low-noise amplifier; noise figure; performance-optimized CMOS; size 0.18 mum; thermal noise; voltage 1.8 V; 1f noise; Bandwidth; Inductors; Low-noise amplifiers; Noise figure; Noise reduction; Performance analysis; Silicon germanium; Termination of employment; Wideband; CMOS; SiGe; distributed amplifier; linearity; low-noise amplifier; noise figure; radio-frequency (RF) integrated circuits; stochastic analysis; ultra-wideband (UWB);
