Title :
A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 MHz Signal Bandwidth
Author :
Li, Zhimin ; Fiez, Terri S.
Author_Institution :
Silicon Labs., Austin
Abstract :
A continuous-time delta-sigma A/D modulator with 5 MS/s output rate in a 2.5 V 0.25 mum CMOS process is presented. The modulator has a fifth-order single-stage, dual-loop architecture allowing nearly one clock period quantizer delay. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero DACs are adopted to reduce clock jitter sensitivity. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. Self-calibration is implemented to suppress current-steering DAC mismatch. Clocked at 60 MHz, the prototype chip achieves 81 dB peak SNR and 85 dB dynamic range with a 12X oversampling ratio. The power consumption is 50 mW.
Keywords :
analogue-digital conversion; circuit tuning; modulators; timing jitter; CMOS process; capacitor tuning; clock jitter sensitivity; continuous-time delta-sigma A/D modulator; current-steering; dual-loop architecture; loop coefficient shifts; multibit quantizer; one clock period quantizer delay; power consumption; Bandwidth; CMOS process; Capacitors; Clocks; Delay; Delta modulation; Dynamic range; Jitter; Prototypes; Signal resolution; Analog-to-digital converter; continuous-time; current calibration; delta-sigma;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2007.903086
