Title :
A 4-GS/s 4-bit Flash ADC in 0.18- μm CMOS
Author :
Park, Sunghyun ; Palaskas, Yorgos ; Flynn, Michael P.
Author_Institution :
Qualcomm Inc., Campbell
Abstract :
A 4-bit noninterleaved flash ADC implemented in 0.18-mum digital CMOS achieves a sampling rate of 4 GS/s. A 32 mum by 32 mum, on-chip differential inductor in each comparator extends the sampling rate without an increase in power consumption. A combination of DAC trimming and comparator redundancy reduces the measured DNL and INL to less than 0.15 LSB and 0.24 LSB, respectively. The measured ENOB with a 100 MHz full-power input is 3.84 bits and 3.48 bits, at 3 GS/s and 4GS/s, respectively. The ADC achieves a bit error rate of less than 10-11 at 4 GS/s.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; digital-analogue conversion; error statistics; 0.18-mum digital CMOS; 4-bit noninterleaved flash ADC; DAC trimming; ENOB; analogue-digital convertor; bit error rate; comparator; digital-analogue convertor; frequency 100 MHz; on-chip differential inductor; size 0.18 mum; storage capacity 3.48 bit; storage capacity 3.84 bit; storage capacity 4 bit; Bandwidth; Energy consumption; Frequency; Inductance; Inductors; Parasitic capacitance; Resistors; Sampling methods; Shunt (electrical); Transconductance; CMOS; DAC trimming; comparator; comparator redundancy; flash analog-to-digital converter; metastability; monolithic inductor; offset correction; regenerative time constant;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2007.903053
