Implementation of digital IC functions with pass transistor switching circuits

The author implements a modified Karnaugh map minimization procedure for pass transistors. The savings in silicon area depends on the transistor count as well as the interconnect structure. Examples demonstrate that considerable savings in silicon area can be achieved by using pass logic instead of gate logic. The savings amount to an 80% reduction in silicon area for NMOS and 6% reduction for CMOS. This means that more die can be fabricated on a silicon wafer, leading to a reduction in product development costs