• DocumentCode
    1110274
  • Title

    Incremental computation of squares and sums of squares

  • Author

    Smith, S.G.

  • Author_Institution
    Dept. of Electr. Eng., Edinburgh Univ., UK
  • Volume
    38
  • Issue
    9
  • fYear
    1989
  • Firstpage
    1325
  • Lastpage
    1328
  • Abstract
    An incremental algorithm for computation of sums of squares is presented that is suitable for both most-significant-bit- (MSB-)first and least-significant-bit- (LSB-)first bit-sequential operation. By exploiting symmetry properties of numerical values and evaluation times in the bit-product matrix, it is shown how incremental multipliers can be converted to perform squaring at reduced hardware cost, and sum of squaring at a hardware cost to that of scalar multiplication. By the elimination of redundant computation, existing hardware modules are either reduced in size or assigned to the evaluation of a second squaring computation. The corresponding hardware architectures are derived from a simple conversion of existing incremental scalar multipliers. This conversion process is less practical on standard serial/parallel or serial-pipeline multipliers. A digit-on-line algorithm is outlined for magnitude extraction operations on plane vectors.<>
  • Keywords
    digital arithmetic; bit-sequential operation; digit-on-line algorithm; hardware architectures; hardware modules; incremental algorithm; incremental multipliers; magnitude extraction operations; plane vectors; scalar multiplication; sums of squares; symmetry properties; Automata; Clocks; Computer architecture; Councils; Counting circuits; Digital arithmetic; Hardware; Iterative algorithms; Pipelines; Symmetric matrices;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.29472
  • Filename
    29472