DocumentCode :
1110302
Title :
Easily Testable Realizations ror Logic Functions
Author :
Reddy, Sudhakar M.
Author_Institution :
Department of Electrical Engineering, University of Iowa
Issue :
11
fYear :
1972
Firstpage :
1183
Lastpage :
1188
Abstract :
Desirable properties of "easily testable networks" are given. A realization for arbitrary logic function, using AND and EXCLUSIVE-OR gates, based on Reed-Muller canonic expansion is given that has many of these desirable properties. If only permanent stuck-at-0 (s-a-0) or stuck-at-1 (s-a-1) faults occur in a single AND gate or only a single EXCLUSIVE-OR gate is faulty, the following results are derived on fault detecting test sets for the proposed networks: 1) only (n/4) tests, independent of the function being realized, are required if the primary inputs are fault-free; 2) only 2n, additional inputs (which depend on the function realized) are required if the primary inputs can be faulty, where n, is the number of variables appearing in even number of product terms in the Reed-Muller canonical expansion of the function; and 3) the additional 2ne inputs are not required if the network is provided with an observable point at the output of an extra AND gate.
Keywords :
Easily testable networks, fault detection, Reed-Muller canonic expressions, single faults, stuck-at-faults.; Circuit faults; Circuit testing; Computer network reliability; Digital systems; Fault detection; Fault tolerance; Logic functions; Logic testing; Network topology; Redundancy; Easily testable networks, fault detection, Reed-Muller canonic expressions, single faults, stuck-at-faults.;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/T-C.1972.223475
Filename :
1672068
Link To Document :
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