Dual-level transmission line model for current flow in metal-semiconductor contacts

Parasitic resistance in the metal-oxide-semiconductor field-effect transistor becomes increasingly important as design rules shrink. The majority of this resistance arises from the contact resistance of the metal-semiconductor interface and the resistance of the semiconductor source and drain regions. The most popular method for deriving current flow in this region is the transmission line model. Though this model has proven quite useful, the severe restriction of one-dimensional current flow will introduce errors in some situations. We formulate and solve a more sophisticated dual-level transmission line model in which we incorporate to first order the two-dimensional nature of the current flow. We discuss this model in terms of an enhancement to the transmission line model and present a detailed comparison of the two models. We find that the dual-level transmission line model produces significant (12 percent) corrections to the transmission line model with source resistivity and thickness and specific contact resistivity typical of 1-µm design rule technologies.