DocumentCode
1110770
Title
Self-Checking Combinational Logic Binary Counters
Author
Dorr, Robert C.
Author_Institution
Bell Telephone Laboratories, Inc.
Issue
12
fYear
1972
Firstpage
1426
Lastpage
1430
Abstract
A high-speed, self-checking count circuit realization is attainable by using combinational logic and parity prediction. The utilization of combinational logic as opposed to sequential logic design generally minimizes the amount of software necessary for routine and diagnostic testing. Count circuits with parity prediction find application in stand-alone, self-checking processors.
Keywords
Binary counter, error detection, integrated circuits, parallel counter, parity generation, parity prediction, self-checking logic.; Application software; Circuit faults; Circuit testing; Combinational circuits; Counting circuits; Electrical fault detection; Fault detection; Hardware; Logic design; Logic testing; Binary counter, error detection, integrated circuits, parallel counter, parity generation, parity prediction, self-checking logic.;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/T-C.1972.223518
Filename
1672111
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