• DocumentCode
    1111600
  • Title

    Sequential delay budgeting with interconnect prediction

  • Author

    Chao-Yang Yeh ; Marek-Sadowska, M.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of California, Santa Barbara, CA, USA
  • Volume
    12
  • Issue
    10
  • fYear
    2004
  • Firstpage
    1028
  • Lastpage
    1037
  • Abstract
    Delay budgeting is a process of determining upper bounds for net delays to guide timing-driven placement. The existing approaches deal de facto only with combinational circuits. However, incorporating retiming into delay budgeting introduces more freedom to optimize sequential circuits. In this paper, we propose an approach for budgeting sequential circuits. We propose a new linear programming formulation for timing-aware sequential budgeting, which guarantees that the clock period constraints are met. We demonstrate the usefulness of our approach in the context of field-programmable gate arrays placement flow. We have performed two experiments. The first experiment compares sequential budgeting with traditional budgeting and retiming. The results show that the new placement flow reduces budget violations by 16% and improves timing by 9%. In the second experiment, we demonstrate methods of interconnect length prediction that are useful to estimate delay and to decide net weighting in sequential budgeting. We compare net delay predictions using traditional delay budgeting, the Donath´s method, and mutual contraction. The results from this experiment show that sequential budgeting, using the new net weighting and predicted delays, can improve circuit speeds on average by 12.29%, compared to traditional timing-driven placement. The new net weighting method also performs better than a uniform weighting method.
  • Keywords
    circuit optimisation; combinational circuits; delay estimation; field programmable gate arrays; linear programming; sequential circuits; timing circuits; Donath method; combinational circuits; delay estimation; field programmable gate arrays; interconnect length prediction; linear programming; net weighting delays; optimize sequential circuits; sequential circuits optimization; sequential delay budgeting; timing aware sequential budgeting; timing driven placement; Algorithm design and analysis; Clocks; Combinational circuits; Delay estimation; Field programmable gate arrays; Integrated circuit interconnections; Sequential circuits; Timing; Upper bound; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2004.827563
  • Filename
    1336848