MeV implants boost device design

Author

Voldman, Steven H.

Author_Institution

IBM Corp., Essex Junction, VT, USA

Volume

11

Issue

6

fYear

1995

fDate

11/1/1995 12:00:00 AM

Firstpage

8

Lastpage

16

Abstract

This high energy technique minimizes soft error rate, latchup, leakage, noise, and ESD in MOSFETs. High energy implant tools reduce process cost and complexity because they eliminate the need for a significant number of process steps and mask levels. Using MeV implant tools for retrograde wells, mask levels and process steps are eliminated. They also reduce metal contamination, thermal stress and wafer warpage. In fact, MeV implanters can substantially reduce the thermal budget from both processing time and temperature. With MeV implanters, there are opportunities to eliminate silicon epitaxy and p+ substrates, 5-to-20 percent cost reduction has been quoted with the migration to low cost wafers and MeV technology

Keywords

MOSFET; electrostatic discharge; ion implantation; semiconductor device noise; thermal stresses; ESD; MOSFETs; high energy technique; ion implantation; latchup; leakage; metal contamination; noise; process cost; retrograde wells; soft error rate; thermal stress; wafer warpage; Contamination; Costs; Electrostatic discharge; Epitaxial growth; Error analysis; Implants; MOSFETs; Silicon; Temperature; Thermal stresses;

fLanguage

English

Journal_Title

Circuits and Devices Magazine, IEEE

Publisher

ieee

ISSN

8755-3996

Type

jour

DOI

10.1109/101.476610

Filename

476610