DocumentCode :
1111980
Title :
Fault Folding for Irredundant and Redundant Combinational Circuits
Author :
To, Kilin
Author_Institution :
Engineering Research Center, Western Electric Company
Issue :
11
fYear :
1973
Firstpage :
1008
Lastpage :
1015
Abstract :
Fault folding is the process of applying test equivalent or test implied relations from a primary output towards the connected primary inputs in order to find a reduced set of faults that cover the set of faults on the intervening network.
Keywords :
Combinational networks, digital fault analysis, fault folding, switching theory, testability relations.; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Industrial relations; Inverters; Logic circuits; Logic testing; Redundancy; Combinational networks, digital fault analysis, fault folding, switching theory, testability relations.;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/T-C.1973.223637
Filename :
1672230
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=1111980
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